Biagio Cosenza

[ home | publications ]
Biagio Cosenza

Biagio Cosenza
Assistant Professor
Dept. of Computer Science
University of Salerno, Italy

Office at UniSa:
Dipartimento di Informatica
Via Giovanni Paolo II, 132
84084 Fisciano (Salerno), Italy
E-mail: bcosenza at unisa.it
Twitter: @biagiocosenza
Scholar, DBLP, ORCID, SCOPUS

Office at TU Berlin:
Sekretariat EN 12, Raum E-N 645
Einsteinufer 17, 10587 Berlin, Germany
AES group, EECS, TU Berlin
Phone: (0049) 30 314 24294
Fax: (0049) 30 314 24943

I am an Assistant Professor (program AIM: Attraction and International Mobility) at the Department of Computer Science, University of Salerno, Italy.
In 2015-2019, I was Senior Researcher at TU Berlin, working with Prof. Ben Juurlink and leading as PI the DFG-funded international project CELERITY. From 2011 to 2015, I was a Post-Doctoral Researcher at the University of Innsbruck, Austria, working with Prof. Thomas Fahringer, contributing to the Insieme Compiler project and the DK-CIM program at the Scientific Computing multidisciplinary platform.
I received my Ph.D. from the University of Salerno in March 2011, supervised by Prof. Vittorio Scarano. There, I was the recipient of several grants and scholarships (HPC-Europa2, HPC-Europa++, DAAD, Cineca ISCRA) and I visited both the HLRS Supercomputing Center and the University of Stuttgart under the supervision of Prof. Carsten Dachsbacher and by Prof. Thomas Ertl.


My research interests include high-performance computing, compiler technology, and software optimization.

News

中国公派留学的申请

Projects Academic Service Research Highlights by Topic Programming models for HPC. Modern HPC systems are difficult to program. Our research focused on high-level programming models, capable to transparently handle data and task parallelism as well as heterogeneity, and to scale on large-scale compute clusters equipped with GPUs and other accelerators. We proposed CELERITY [Euro-Par19], a C++ SYCL-based programming supported by a distributed runtime system, integrated with a compiler. Under the hood, CELERITY uses two representations for scheduling and optimization: a task graph and a command graph [ICS13]. Automatic tuning. Software often exposes parameters that affects performance and other metrics. Parallel programs for modern computer architectures requires the tuning of a large number of code variants. My research focuses on autotuners for parallel optimization, in particular on machine learning approaches integrated into compiler. Examples are classification for automatic task partitioning [ICS13] , regression for GPU frequency scaling [ICPP19] , and ordinal regression for stencil computation [IPDPS17]. Approximate computing. Many applications provide inherent resilience to some amount of error and can potentially trade accuracy for performance. Our research focused on software approaches for approximate computing, such as kernel perforation, and their optimization for GPU architectures [CGO18]. Vectorization. Modern processors come equipped with Single Instruction Multiple Data (SIMD) instructions. Examples are Intel AVX, ARM NEON, and recent Vector Length Agnostic ISAs such as ARM’s Scalable Vector Extensions (SVE). Our research investigated different aspects of efficient code generation for vectorization, such as cost modeling [MASCOTS19] and control flow [SCOPES18] . Visit the publication page for a complete list of publications. Teaching University of Salerno TU Berlin University of Innsbruck
[ ISIS Lab | Dept. of Computer Science | University of Salerno ]